CVA Network-on-Chip Project
Project Overview
Networks on Chip (NoCs) become more important as technology feature size continues to shrink. Understanding NoC and system network differences leads to efficient NoC architectures. Custom circuitry must be developed and standardized.
We will employ a bottom-up approach. Modeling and improving circuits will help us derive estimates to aid higher-level decisions. The goal is to close the performance gap with the ideal interconnect.
Circuits
Channels can benefit greatly from custom circuit design. We plan to investigate low-swing signaling, high-bandwidth transmission and elastic buffering.
Preliminary results have shown that operating channels at a 50 mV or lower differential swing yields a 20x improvement in energy efficiency over standard full-swing repeaters.
Flow Control
We will evaluate the popular packet switching against elastic buffering and circuit switching. We will choose an optimal topology for each one. Elastic buffering and circuit switching remove all buffering from the routers.
Evaluations of elastic buffering suggest it can yield significant power savings and latency up to equal to packet switching.
Microarchitecture
We are investigating various microarchitectural cost-performance tradeoffs for NoC routers. In particular, we are evaluating different allocator architectures in terms of matching efficiency, cost (delay/area/power), and their impact on network-level performance; we plan to use the insights gained from this study as a basis for developing improved allocation mechanisms.
Future work will address other important aspects of router microarchitecture, including optimized approaches to buffer management.
To facilitate detailed cost-benefit analysis of proposed microarchitectural enhancements, we have developed a highly parameterized, fully synthesizable RTL implementation of a state-of-the-art VC router. We are currently in the process of validating the design; once validation is complete, we plan to release the full Verilog source code to the research community as open source.
Topologies
Most applications use simple topologies (e.g. 2D mesh) with a large network diameter and average hop count. The flattened butterfly topology guarantees only two hops to every destination (at 2D) with minimal routing. This yields latency and power savings.
We will also investigate duplicating links in every direction, and dividing the network into sub-networks.