wiki:Publications
Last modified 3 years ago Last modified on 10/24/13 10:17:46
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Publications

[ 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2001 | Talks | Posters ]


2013

Nan Jiang. Congestion Control and Adaptive Routing in Large-Scale Interconnection Networks. PhD thesis, Stanford University, March 2013. [ http ]

Nan Jiang, Daniel U Becker, George Michelogiannakis, James Balfour, Brian Towles, John Kim and William J Dally. A Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator. In Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software, 2013. [ .pdf​, doi ]

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2012

Daniel U Becker, Nan Jiang, George Michelogiannakis and William J. Dally. Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks. In Proceedings of the 30th IEEE International Conference on Computer Design, 2012. [ .pdf, doi ]

Daniel U Becker. Efficient Microarchitecture for Network-on-Chip Routers. PhD thesis, Stanford University, August 2012. [ http ]

George Michelogiannakis. Energy-Efficient Flow-Control for On-Chip Networks. PhD thesis, Stanford University. June 2012. [ http ]

Nan Jiang, Daniel U Becker, George Michelogiannakis and William J Dally. Network Congestion Avoidance Through Speculative Reservation. In Proceedings of the 18th International Symposium on High-Performance Computer Architecture, 2012. [ .pdf, doi ]

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2011

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011. [ .pdf, doi ]

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Computer Architecture Letters, June 2011. [ .pdf, doi ]

George Michelogiannakis, Daniel U Becker and William J Dally. Evaluating Elastic Buffer and Wormhole Flow Control. IEEE Transactions on Computers, 60(6):896-903, June 2011. [ .pdf, doi ]

Nan Jiang, Daniel U Becker, George Michelogiannakis and William J Dally. Performance Implications of Age-Based Allocation in On-Chip-Networks. Technical Report 129, Concurrent VLSI Architectures Group, Stanford University, May 2011. [ .pdf ]

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. Technical Report 128, Concurrent VLSI Architectures Group, Stanford University, April 2011. [ .pdf ]

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2010

George Michelogiannakis, Daniel Sanchez, William J Dally and Christos Kozyrakis. Evaluating Bufferless Flow Control for On-Chip Networks. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip, 2010. [ .pdf ]

Daniel Sanchez, George Michelogiannakis and Christos Kozyrakis. An Analysis of Interconnection Networks for Large Scale Chip Multiprocessors. ACM Transactions on Computer Architecture and Code Optimization, April 2010. [ .pdf ]

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2009

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. In Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ .pdf ]

Daniel U Becker and William J Dally. Allocator implementations for network-on-chip routers. In Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ .pdf, doi ]

George Michelogiannakis, James Balfour and William J Dally. Elastic-buffer flow control for on-chip networks. In Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture, 2009. [ .pdf ]

George Michelogiannakis and William J Dally. Router designs for elastic buffer on-chip networks. Technical Report 125, Concurrent VLSI Architectures Group, Stanford University, 2009. [ .pdf ]

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2008

George Michelogiannakis, James Balfour and William J Dally. Elastic buffer networks-on-chip. Technical Report 124, Concurrent VLSI Architectures Group, Stanford University, 2008. [ .pdf ]

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2007

John D Owens, William J Dally, Ron Ho, D N Jayasimha, Stephen W Keckler and Li-Shiuan Peh. Research challenges for on-chip interconnection networks. IEEE Micro, 27(5):96-108, 2007.

John Kim, James Balfour and William J Dally. Flattened butterfly topology for on-chip networks. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007.

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2006

James Balfour and William J Dally. Design tradeoffs for tiled cmp on-chip networks. In Proceedings of the 20th annual International Conference on Supercomputing, 2006.

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2001

William J Dally and Brian Towles. Route packets, not wires: On-chip inteconnection networks. In Proceedings of the 38th Conference on Design Automation, 2001.

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Talks

Daniel U. Becker. Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks. Presented at ICCD '12, Montreal, QC, Canada, Sep. 30-Oct. 3, 2012. [ .pptx ]

Daniel U. Becker. Efficient Microarchitecture for Network-on-Chip Routers. Thesis defense talk. Stanford, CA, August 21, 2012. [ .pptx ]

George Michelogiannakis. Evaluating Bufferless Flow Control for On-Chip Networks. Presented at NOCS '10, Grenoble, France, May 3-6, 2010. [ .ppt ]

Daniel U. Becker. Allocator Implementations for Network-on-Chip Routers. Presented at SC '09, Portland, OR, Nov. 14-20, 2009. [ .pptx ]

George Michelogiannakis. Router Designs for Elastic Buffer On-Chip Networks. Presented at SC '09, Portland, OR, Nov. 14-20, 2009. [ .ppt ]

Daniel U. Becker. Networks on Chip: Router Microarchitecture & Network Topologies. Presented at ST Microelectronics, Crolles, France, Oct. 13, 2009. [ .pptx ]

George Michelogiannakis. Elastic Buffer Flow Control. Presented at ST Microelectronics, Crolles, France, Oct. 13, 2009.

George Michelogiannakis. Elastic-buffer flow control for on-chip networks. Presented at HPCA-15, Raleigh, NC, Feb. 14-18, 2009. [ .ppt ]

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Posters

Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks. Presented at the Pervasive Parallelism Lab Retreat, Spring 2012 [ .pdf ]

Buffer Organization Trade-offs in On-Chip Networks. Presented at the Pervasive Parallelism Lab Retreat, Spring 2011 [ .pdf ]

Enabling Technology for On-Chip Networks. Presented at the 2010 Computer Forum, Stanford, CA, April 28, 2010. [ .pdf ]

Enabling Technology for On-Chip Networks. Presented at the 2009 Advanced Computing Systems Research Program Workshop, Annapolis, MD, Sep. 16-17, 2009. [ .pdf ]

Enabling Technology for On-Chip Networks. Presented at the Stanford CIS Meeting, Spring 2009. [ .pdf ]

Enabling Technology for On-Chip Networks. Presented at the Stanford CIS Meeting, Fall 2008. [ .pdf ]

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