Last modified 4 years ago Last modified on 12/20/13 20:03:35

Open Source Network-on-Chip Router RTL

In order to facilitate detailed evaluations of the delay, power and area tradeoffs associated with different microarchitectural design choices, we have developed a parameterized RTL implementation of a state-of-the-art VC router. In doing so, we followed three primary design goals:

  • To provide a generic, flexible router implementation that, through extensive use of parameterization, is able to support a wide variety of configurations in terms of router radix, number of VCs, allocators and other key design parameters, enabling rapid design space exploration.
  • To allow for individual configurations to be synthesized into reasonably efficient hardware implementations using industry-standard design flows, enabling detailed cost and performance evaluations.
  • To provide a modular design that facilitates extensibility by interested third parties, enabling them to leverage the existing code base for microarchitectural research.

The router model is implemented in the industry-standard Verilog hardware description language, and includes programmable pseudo-random traffic generators and signature analysis modules, which facilitate the setup of simple test networks.

The current development branch can be accessed through our web-based repository browser or via direct access to the subversion repository. Please refer to our online bug tracking system for known issues and limitations.

We also maintain two mailing lists related to the router RTL: The router-users list is intended for general discussion and questions relating to the use of the router RTL, while router-devel is for development-related discussions.

For further information regarding the Open Source NoC Router RTL, please contact Daniel Becker.

This work was supported in part by a Michael J. Flynn Stanford Graduate Fellowship, in part by the National Science Foundation under grant CCF-0702341 and in part by the National Security Agency under contract H98230-08-0272-P-3.

If you use our Open Source NoC Router RTL in your research, we would appreciate the following citation in any publications to which it has contributed:

Daniel U. Becker. Efficient Microarchitecture for Network-on-Chip Routers. PhD thesis, Stanford University, August 2012. [ http ]